1. Field of the Invention
The present invention relates to circuits for performing divide operations.
2. Description of the Related Art
Many applications require a circuit designer to implement a mathematical algorithm or evaluate a mathematical equation. Most operations of these algorithms may be performed by circuits which perform the simple operations of add, subtract, multiply and divide. Addition and subtraction are the simplest operations; signals may be simply combined in an adder implemented with, for example, a unity gain amplifier in the analog domain and counters or shift registers in the digital domain. A subtract operation is usually performed by an adder in either the analog or digital domain which complements the signal to be subtracted. A multiply operation by a multiplier is also easily implemented, either through transistor/diode circuits in the analog domain or by counters and shift registers in the digital domain. A divide operation, however, is more difficult to implement. FIG. 1A shows a divider circuit of the prior art, known as an array divider, and FIG. 1B illustrates a controlled add/subtract cell (CAS) of the array divider of FIG. 1A. A typical divider circuit of the prior art may implement a sequential partial remainder algorithm using an array of add/subtract cells. In FIG. 1A, x.sub.0, x.sub.1, . . . , x.sub.6 are the bit values of the dividend, d.sub.0, d.sub.1, d.sub.2, d.sub.3 are the bit values of the divisor, q.sub.0, q.sub.1, q.sub.2, q.sub.3 are the bit values of the quotient, and r.sub.0, r.sub.1, r.sub.2, r.sub.3 are the bit values of the remainder. As shown in FIGS. 1A and 1B, a divider circuit is quite complex. Further, typical applications are now often implemented in an integrated circuit (IC), and the IC usually has many large arrays of multipliers at various locations on the IC already available to the circuit designer as a consequence of the overall IC design process. Also, these multiplier designs are available to the circuit designer in an IC design library. A divider, on the other hand, is difficult to implement on an IC, and is not generally available to the circuit designer without specifically designing the divider at a particular location on the IC. Such design also tends to require more IC real estate than the multiplier circuits.